1. Field of the Invention
The present invention is related to interconnect busses of computer systems and in particular to dynamically connecting multiple devices to an interconnect bus such that only a single one of the multiple devices is connected to the interconnect bus at any time.
2. Description of the Related Art
Many computer systems use interconnect busses for multiple types of traffic. In addition, other embedded digital systems use interconnect busses for connecting devices in the embedded digital system.
Typical interconnect busses that share a common clock will naturally experience a reduction in electrical loading, a restriction in layout, or both as the shared common clock frequency increases. Fewer numbers of faster devices than slower devices can be connected to a given bus segment. For example, an interconnect bus running according to the PCI-X specification can support four devices running at 66 MHz, two at 100 MHz, and only a single device running at 133 MHz on any given bus segment.
Such a limitation may impose costs on system designers. Servers and other computer systems typically have a number of slots for interconnect devices. Limiting a bus segment to a single interconnect device means that each slot typically has its own sourcing bridge/host bridge per slot, increasing total system costs. In addition, the requirement for multiple bridges imposes additional space costs. Allowing a system designer an option to increase the electrical loading on a bus segment without adversely affecting performance, such as slowing device speeds, thereby reducing bandwidth, would be desirable.